Hardware posible solutions
From Openjtag
Projected JTAG applications:
Accessing processor core (INTEST), for debugging using the built-in Debug Support Unit (DSU).
Accessing target system components over CPU/uC pins (EXTEST), for example SPI, [=I2C=], parallel flash etc.
Identified speed critical issues:
Bit/Clock rate. The raw clock rate a JTAG interface is able to sustain (TCK rate).
Read-back latency. If the JTAG application needs to read TDO data, this becomes quickly as important as the TCK rate. Not an issue for EXTEST applications like SPI writes (to flash etc.), but critical for debuggers and SPI reads.
The JTAG host interface could be realized with...
Parallel port
excludes legacy-free systems low read-back latency
Direct JTAG connection (Wiggler)
slow, but simple estimated TCK rate: ??
Custom hardware attached to parall port
requires custom logic, custom protocol estimated maximum transfer rate: ?? max TCK rate: ??
USB port
higher read-back latency, caused by USB frame concept: aone frame: 1ms (Full-Speed); 125us (High-Speed) one TDO read cycle requires at least 2ms/250us
I don't think the frame concept will cause a problem if we're actually transferring the bits via bulk transfer and using a (at least relatively) dedicated interface. Isochronous packets are programmed for particular subframes in the standard (e.g. OHCI) interfaces to get a particular level of service, but there is nothing that prevents you from polling them in every subframe. After servicing programmed requests for isochronous packets and interrupts packets in a particular subframe, the rest is dedicated to bulk transfers. If there's only one bulk transfer requesting service for the interface, it gets all the slack.
[|FTDI 2232C] aUSB peripheral, allows direct bit-banging to the JTAG lines, no custom hardware required
EZ-USB was bought out by Cypress. The newer chips handle high speed. But of course it isn't possible for the processor to keep up with 480Mps. Consequently, relatively primitive interface state machine logic is provided that essentially allows data to pass through the USB engine out to external logic without (necessarily) involving the processor. The processor then becomes useful just for configuration and exception processing. Consequently, we could run closer to interface speed (less protocol overhead).
My thoughts on this:
1. Make a "dongle style" USB JTAG interface that has the 8051 control processor doing bit
banging. This will give a relatively slow transfer rate, but will get us up and running
relatively quickly.
2. Using the same processor, add a CPLD to interface with the GPIF (General Purpose Interface
Engine). The GPIF provides data transfer between the USB interface and the CPLD. The CPLD
is programmed with a state machine to provide the proper signals at the 4 JTAG lines,
which obviously includes (preferably different rates for) TCK as well as providing for different
voltage levels (I'm unsure exactly how the voltage is supplied for the JTAG interface itself).
3. An added benefit of having done #1 first, is that with many CPLDs being programmed via
JTAG, we can build the bit-banging JTAG into the final interface to both bootstrap and update
the CPLD without needing an external JTAG interface. The firmware for the EZUSB can be
either loaded every time (not that slow given USB 2.0 and a high speed interface) or we can
include an EEPROM on board the interface.
Supports 3.3V and 5V logic
FTDI offers sample application for JTAG: http://www.ftdichip.com/Projects/MPSSE.htm There is an open source cross-platform library for accessing the FTDI chips, so the JTAG project can be cross-platform: http://www.intra2net.com/opensource/ftdi/
Potential FTDI boards: [|DLP-2232M] is an evaluation module from FTDI. It has been used for development by the openjtag team. An additional 3.3V regulator might be needed. Cost: 19.50 about US$35
[|EZNIOSUSB] is a daughter board for NIOS development boards but could be used stand-alone. Has a 3.3V regulator onboard. Cost: US$99 [|CableMAX Dual USB to Serial adapter] Has been found to contain a 2232C. Cost: US$40
FPGA solution
Xilinx Spartan 3 dev board http://www.xilinx.com/products/spartan3e/s3eboards.htm http://www.digilentinc.com/info/S3Board.cfm the geep-b fpga board http://www.gnugeep.org this board is 1 a GPL board but is idealy suited to the jtag application estimated cost £105 approx thats $200usd 20/3/07
another fpga based solution that looks like it would be ideal http://www.enterpoint.co.uk/moelbryn/tarfessock1.html as soon as its avalable that is
