High speed jtag adaptor
From Openjtag
High speed jtag adaptor
this is the main goal of the project
the idea is to use a FPGA based card that has a large amount of buffer ram the GEEP-B i developed to fit this need
in order to achive the high speed rates required it was seen that we needed a fast fpga based board with its own ram but the cost implications of desining such a board for just this project and the time invested in doing it led to the idea to develop a genaral purpous fpga card that could be used for a wide number of applications besides just this project
the geep-b at the time of writing this is at the first prototype stage , and we are currently waiting delivery of the first batch of pcbs , once the main geep-b units are operational from the hardware side it should just involve the development of a simple adaptor board for the appropriate jtag connector and level translators
the main geep-b is a 4 layer pcb , it was designed with home construction in mind and although uses surface mount devices it does not use any BGA packaged devices
the geep-boad uses a concept idea that i have been working on for a number of years to provide a simple yet flexible method to modular i/o and interfaceing using fpga based devices allowing it to be used as a modular component in custom designs
the main geep-b board is estimated to cost £105 ($200) at one of parts prices that is including the pcb ( but at 10 of price for the pcb)
for this project it will require the development of the jtag to i/o chan adaptor but a $50 estimated cost would cover the cost of parts including pcb for a set of all the jtag adaptors that should cover most of the comman jtag header formats
there are another of usefull adaptors planned for the geep-b that are relivant to this project theres a la adaptor that should let the geep-b opperate as a 16 input logic analizer with 100M samples second and a DSO adc adaptor that should let the geep-b operate as a 100M/samples per second digital storage osilioscope the geep-b's can be linked together to extend there funtionalaty and number of i/o chans
for jtag it should have no real problem with jtag clocking up to 80mhz , and hopefully should mangage 100mhz it has 32mb or 64mb of sdram that would provide a suitable buffer space for any vhdl bit stream or a large debug trace
originaly the design has changed a number of times from the aztag design original mentioned here on this site and there has been some unavoidable delays in developing the design ,, partly dew to me moving house and living in tempory accomodation for a few months but things are getting back on track again at the moment
although the geep-b was designed with this project in mind i decided that as it is more of a genaral purpouse board to make its development seperate from the jtag project , as it will include lots of other related interface modules that may be used with it that are not relivent to this project, so better to keep it seperate so as not to have this project supporting all the apps and modules that may be used with the geep-b , that is more than just jtag or related stuff
the geep-b site is http://www.gnugeep.org (project abandoned)
David (aka AchiestDragon) 20/3/07
update 17 june 09 :- the geep-b project was abandoned some time ago although the reasoning for needing such a project is still valid
although the geep-b project has been canceled and i nolonger have time to particiate in the project there has been a couple of interesting fpga modules made available by a commertial vendor that would be suitable for this application requireing only the vhdl code and a simple interface that would be ideal to use inplace
the http://www.enterpoint.co.uk/component_replacements/craignell2.html seems to be the best of the bunch
David (aka AchiestDragon) 17 june 09
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